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An AVS HDTV video decoder architecture employing efficient HW/SW partitioning

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4 Author(s)
Huizhu Jia ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing ; Peng Zhang ; Don Xie ; Wen Gao

In this paper, we propose an optimized real-time AVS (a Chinese next-generation audio/video coding standard) HDTV video decoder. The decoder has been implemented in a single SoC with HW/SW partitioning. AVS algorithms and complexity are first analyzed. Based on the analysis, a hardware implementation of the MB level 7-stage pipeline is selected. The software tasks are realized with a 32-bit RISC processor. We further propose the optimization of interface and RISC processor based on the proposed architecture. The AVS decoder (RISC processor and hardware accelerators) is described in high-level Verilog/VHDL hardware description language and implemented in a single-chip AVS HDTV real-time decoder. At 148.5 MHz working frequency, the decoder chip can support real-time decoding of NTSC, PAL or HDTV (720p@60 frames/s or 1080i@60 fields/s) bit-streams. Finally, the decoder has been fully tested on a prototyping board

Published in:

IEEE Transactions on Consumer Electronics  (Volume:52 ,  Issue: 4 )