By Topic

A hardware implementation for full-search motion estimation of AVS with search center prediction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Shuo Yao ; Zhejiang Univ., Hangzhou ; Hai-Jun Guo ; Lu Yu ; Ke Zhang

This paper presents a full search motion estimation algorithm with search center prediction for AVS and the VLSI architecture to realize the algorithm. The proposed algorithm achieves comparable performance in coding efficiency with the anchor algorithm, whereas has low storage requirement, low required bandwidth and low complexity for the hardware implementation. The proposed architecture adopts 1-D PE arrays architecture and can perform variable block size motion estimation with 70 k logic gates and 24 kbits on-chip memory. The architecture achieves best tradeoff in terms of speed and hardware cost. The design can satisfy real-time encoding for AVS high definition application of 1280times720 picture size at 60 fps

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:52 ,  Issue: 4 )