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Exploring ASIC design space at system level with a neural network estimator

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5 Author(s)
P. Ellervee ; KTH-Electron., R. Inst. of Technol., Kista, Sweden ; A. Jantsch ; J. Oberg ; A. Hemani
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Estimators are critical tools in carrying out architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows the description of arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and present results of the first experiments made with realistic design examples

Published in:

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Date of Conference:

19-23 Sep 1994