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A 200 ps 0.5 μm CMOS gate array family with high speed modules

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10 Author(s)
Y. Nishio ; Hitachi Res. Lab., Ibaraki, Japan ; H. Hara ; M. Iwamura ; Y. Kaminaga
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A 0.5 μm CMOS gate array family with high speed modules is discussed. Measured access time of the 8 Kbit 2-port metallized RAM is 6.3 ns. Simulated access time of the 16 Kbit diffused RAM is 5.5 ns. Propagation delay time of the 2-input NAND is 200 ps at a standard load. Use of high performance internal logic circuits, high speed compiled RAM, improved GTL (Gunning Transceiver Logic), and PLL (Phase Locked Loop) realizes operation of over 100 MHz at 3.3 V. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment

Published in:

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Date of Conference:

19-23 Sep 1994