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Performance-driven technology mapping for LUT-based FPGAs

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3 Author(s)
Hyunchul Shin ; Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea ; Chunghee Kim ; Younguk Yu

An effective and iterative optimization technique is developed for technology mapping of lookup table based field programmable gate arrays. In the algorithm, minimal depth of a given optimized Boolean network is found and then the given cost function is minimized by “sweeping” nodes of the given Boolean network without increasing the depth optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that the approach is very promising

Published in:

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Date of Conference:

19-23 Sep 1994