Designing a high complexity microprocessor using the Alliance CAD system

This paper presents the design methodology for a Superscalar 128-bit Very Long Instruction Word (VLIW) processor. A full set of portable cell libraries, macro-block generators associated with complex and advanced tools, such as logic synthesis, functional abstractor, formal proof tool and data-path compiler have been used in order to achieve a fast design cycle, and still maintain a high level of integration and performance. The final circuit contains about 875,000 transistors with a die size of 14.6 * 14.6 mm/sup 2/ in a 0.8 /spl mu/m process.<
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