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Designing a high complexity microprocessor using the Alliance CAD system

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3 Author(s)
A. Greiner ; Lab. MASI, Univ. Pierre et Marie Curie, Paris, France ; L. Lucas ; F. Wajsburt

This paper presents the design methodology for a Superscalar 128-bit Very Long Instruction Word (VLIW) processor. A full set of portable cell libraries, macro-block generators associated with complex and advanced tools, such as logic synthesis, functional abstractor, formal proof tool and data-path compiler have been used in order to achieve a fast design cycle, and still maintain a high level of integration and performance. The final circuit contains about 875,000 transistors with a die size of 14.6 * 14.6 mm2 in a 0.8 μm process

Published in:

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Date of Conference:

19-23 Sep 1994