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Leveraging Wire Properties at the Microarchitecture Level

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5 Author(s)

In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy

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Micro, IEEE  (Volume:26 ,  Issue: 6 )