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Customizable FPGA-based architecture for video applications in real time

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2 Author(s)
Saldana, G. ; Dept. of Comput. Sci., National Inst. for Astrophys., Opt. & Electron., Puebla ; Arias-Estrada, M.

This paper describes an efficient reconfigurable architecture suitable for full-search block-matching motion estimation with minimum latency and maximum throughput, based on a systolic array. The architecture is characterized by low memory bandwidth requirements, a modular and highly flexible structure based on Router elements to handle processing blocks interconnection from a high level pipeline scheme. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. The functionality has been extended to support operations involved in some low-level algorithms which include image filtering, matrix-matrix multiplication, morphological operations and pyramid processing. The architecture provides a flexible solution under real-time constraints and constitutes a platform to pursue the implementation of higher complexity algorithms. Preliminary results show that a peak performance in the order of GOPS can be achieved

Published in:

Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on

Date of Conference:

Dec. 2006

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