Referenced Items are not available for this document.
The area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse grain hardware. Since the field is still in its infancy, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents analysis of the advanced encryption standard (Rijndael), which is then implemented on a coarse grain reconfigurable platform (MorphoSys). We provide details of mapping Rijndael and present an analysis to highlight the apparent bottlenecks. We suggest methods of upgrading and enhancing the MorphoSys hardware accordingly
Published in:
Signal Processing and Information Technology, 2006 IEEE International Symposium on
Date of Conference: Aug. 2006
- Page(s):
- 496 - 501
- E-ISBN :
- 0-7803-9754-1
- Print ISBN:
- 0-7803-9753-3
- INSPEC Accession Number:
- 9387947
- Conference Location :
- Vancouver, BC
- Digital Object Identifier :
- 10.1109/ISSPIT.2006.270852
- Product Type:
- Conference Publications
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