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Fair Queuing Memory Systems

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4 Author(s)
Nesbit, K.J. ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI ; Nidhi Aggarwal ; Laudon, J. ; Smith, J.E.

We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fair queuing scheduling algorithms. The memory scheduler is fair and provides quality of service (QoS) while improving system performance. On a four processor CMP running workloads containing a mix of applications with a range of memory bandwidth demands, the proposed memory scheduler provides QoS to all of the threads in all of the workloads, improves system performance by an average of 14% (41% in the best case), and reduces the variance in the threads' target memory bandwidth utilization from .2 to .0058

Published in:

Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on

Date of Conference:

9-13 Dec. 2006