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Modeling intermediate tests for fault-tolerant multichip module systems

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2 Author(s)
Sungsoo Kim ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Lombardi, Fabrizio

This paper presents analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCM's) for massively parallel computing (MPC). In the proposed approaches, we employ both a novel Markov model and a so-called working-test-set to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests to meet MCM quality requirements effectively. Several strategies for appropriately testing fault-tolerant MCM's have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRTWS (Least Recently Tested in WS) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCM's more accurately and efficiently, thereby improving upon the reliability and quality of the entire system

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:18 ,  Issue: 3 )