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An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

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11 Author(s)
Kyu-hyoun Kim ; IBM T. J. Watson Res. Center, Yorktown Heights, NY ; Hoe-Ju Chung ; Woo-Seop Kim ; Moonsook Park
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This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 1 )