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Synthesis of UP-DOWN Counters

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1 Author(s)
Kain, R.Y. ; Dept. Elec. Engrg., University of Minnesota, Minneapolis, Minn. 55455.

IN this paper we will describe an algorithm for the decomposition of UP-DOWN counters. The constituents of the decomposed counters will be UP-DOWN counters of small modulus and small amounts of combinatorial logic. The main advantage accruing from this decomposition technique is that only a small number of building blocks is required to build counters with any modulus. We will begin the discussion by developing analysis techniques for particular interconnections of UP-DOWN counters. Following this, a general technique for the synthesis of an UP-DOWN counter with any modulus will be given. Only binary and ternary UP-DOWN counters and a small amount of combinatorial logic will be required.

Published in:

Electronic Computers, IEEE Transactions on  (Volume:EC-16 ,  Issue: 2 )

Date of Publication:

April 1967

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