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Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application

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3 Author(s)
Yu-Han Chen ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Tung-Chien Chen ; Liang-Gee Chen

In this paper, a power-scalable H.264 encoding system is provided with the efforts on both the algorithm and the architecture levels. For a start, a motion estimation (ME) pre-skip algorithm is adopted as a system-level power-scalable algorithm. In order to realize a dedicated hardware, a novel reconfigurable macro-block (MB) pipelining architecture is proposed. It can improve not only system flexibility but also hardware efficiency. Besides, it is also beneficial for power management with module-level gated clock insertion. According to simulation results, the proposed H.264 encoder can support power-scalable functionality in the range of about 20 to 90 mW with graceful quality degradation

Published in:

Multimedia and Expo, 2006 IEEE International Conference on

Date of Conference:

9-12 July 2006

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