A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

A RHBD topology for digital phase-locked loops (DPLLs) has been developed for single-event transient (SET) mitigation. By replacing the vulnerable current-based charge pump with a SET-resistant tri-state voltage-switching charge pump and a low-pass filter, the DPLL single-event susceptibility was considerably reduced, while simultaneously decreasing the lock-in time of the DPLL. The design results in a decreased area requirement with minimal impacts on phase jitter and power consumption. Furthermore, the design eliminates the charge pump as the most vulnerable module and significantly hardens the DPLL