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An Area and Power Efficient Radiation Hardened by Design Flip-Flop

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2 Author(s)
Knudsen, J.E. ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ ; Clark, L.T.

A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm2 /mg) at VDD=1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described

Published in:

Nuclear Science, IEEE Transactions on  (Volume:53 ,  Issue: 6 )

Date of Publication:

Dec. 2006

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