InSyn: integrated scheduling for DSP applications

We present the InSyn algorithm for high-level synthesis of DSP applications. InSyn combines allocation and scheduling of functional, storage, and interconnect units into a single phase and uses the following unique optimizations. (i) The concept of register states (free, busy, and undecided) is used for optimizing registers in a partial schedule where lifetimes of data values are not yet available. (ii) Reusable data values and broadcast are used to alleviate bus contention. (iii) InSyn can alternate between performance-guided and resource-guided measures. For example, InSyn can forgo its priority in favor of completing partially evaluated paths when the availability of allocated registers becomes low. (iv) InSyn ran selectively increase execution time of noncritical operations to alleviate bus contention. (V) InSyn can optimize and trade off distinct (functional units, interconnect, and registers) resource sets concurrently leading to more area-delay efficient designs. (vi) InSyn utilizes estimation tools towards resource allocation, design space pruning, and evaluation of synthesized designs. The experiments show that the features incorporated in inSyn result in very good designs