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A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering

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4 Author(s)
Tze-Yun Sung ; Dept. of Microelectron. Eng., Chung Hua Univ., Hsinchu ; Yaw-Shih Shieh ; Chun-Wang Yu ; Hsi-Chin Hsin

High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3D rotation for high throughput 3D vector interpolation are presented in this paper. The primitives are based on the CORDIC algorithm. The proposed architecture of the 3D vector interpolator using redundant CORDIC arithmetic is presented in this paper. The high-throughput 3D vector interpolator is implemented by VLSI

Published in:

Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on

Date of Conference:

Dec. 2006

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