By Topic

A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tze-yun Sung ; Chung Hua University, Taiwan ; Yaw-shih Shieh ; Chun-wang Yu ; Hsi-chin Hsin

High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3D rotation for high throughput 3D vector interpolation are presented in this paper. The primitives are based on the CORDIC algorithm. The proposed architecture of the 3D vector interpolator using redundant CORDIC arithmetic is presented in this paper. The high-throughput 3D vector interpolator is implemented by VLSI

Published in:

2006 Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'06)

Date of Conference:

Dec. 2006