Cart (Loading....) | Create Account
Close category search window
 

A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Tze-Yun Sung ; Dept. of Microelectron. Eng., Chung Hua Univ., Hsinchu ; Yaw-Shih Shieh ; Chun-Wang Yu ; Hsi-Chin Hsin

High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3D rotation for high throughput 3D vector interpolation are presented in this paper. The primitives are based on the CORDIC algorithm. The proposed architecture of the 3D vector interpolator using redundant CORDIC arithmetic is presented in this paper. The high-throughput 3D vector interpolator is implemented by VLSI

Published in:

Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on

Date of Conference:

Dec. 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.