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A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

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3 Author(s)
Dechu, S. ; Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL ; Goparaju, M.K. ; Tragoudas, S.

Compared to CMOS logic gates, threshold logic gates are more susceptible to manufacturing inaccuracies. These inaccuracies may inadvertently affect the functionality of the gate. Hence it is very much important to consider the manufacturing defects during the design of gates using threshold logic principle. This paper defines a metric which indicates the degree of tolerance of a designed gate to the manufacturing inaccuracies. Experimental results have been presented for several gates

Published in:
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on

Date of Conference: 4-6 Oct. 2006

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