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1.2V and 8.6mW CMOS differential receiver front-end with 24 dB gain and -11dBm IRCP

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4 Author(s)
D. Huang ; Dept. of Electr. Eng., Univ. of California, CA ; R. Wong ; C. Chien ; M. -c. f. Chang

A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P1 dB compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm2)

Published in:

Electronics Letters  (Volume:42 ,  Issue: 25 )