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An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications

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3 Author(s)
Ching-Che Chung ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu ; Pao-Lung Chen ; Chen-Yi Lee

This paper presents an all-digital delay-locked loop (DLL) for DDR SDRAM controller applications. The presented all-digital, cell-based, DLL-based five-phase multi-phase clock generator can generate the required fixed timing delay (tSD) for DDR SDRAM controller to capture the output data (DQ) correctly. The proposed DLL-based multi-phase clock generator architecture can lock to the harmonic of input clock period and still get a correct multi-phase clock output. Hence the design challenges to build a high resolution delay line with minimum intrinsic delay can be reduced. Simulation results and chip measurement results show that the proposed DLL can generate desired tSD delay with error < 7.6%. The power consumption of the proposed DLL is 4.1mW (at DDR-200) and is 9.0mW (at DDR-400)

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006