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A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling

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6 Author(s)
Tsung-Chu Huang ; Dept. of Electron. Eng., Nat. Changhua Univ. of Educ. ; Jing-Chi Tzeng ; Yuan-Wei Chao ; Ji-Jan Chen
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Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006