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A Partition-Based Voltage Scaling Algorithm Using Dual Supply Voltages for Low Power Designs

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4 Author(s)
Hung Hsie Lee ; Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li ; Sung Han Tsai ; Jun-Cheng Chi ; Mely Chen Chi

We proposed an effective voltage scaling technique to assign the supply voltage to gates in the circuit of dual power supplies. The algorithm is composed of a greedy voltage assignment phase and an iterative voltage re-assignment refinement phase. It reduces the total power without performance degradation. We apply the algorithm to several test cases. It shows that on average the total power saved is 54.7%. Compared to the GECVS technique (Kulkami, 2004), our algorithm reduces the number of level converters by 23.2% and the power consumption by 5.5%. The experimental result also shows the distribution of slack in the original and the power optimized designs. It shows that majority slacks of the gates are reduced. The algorithm utilizes the slack of gates to scale down the supply voltage of the gates such that the power consumption is reduced

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006