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61.5mW 2048-bit RSA Cryptographic Co-processor LSI based on N bit-wised Modular Multiplier

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7 Author(s)
Toru Hisakadot ; Graduate School of IPS, Waseda University, Japan, 2-7, Hibikino, Wakamatsu-ku, Kitakyushu, 808-0135, Japan; NEC Corporation, 1753, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, 211-8666, Japan, ; Nobuyuki Kobayashi ; Satoshi Goto ; Takeshi Ikenagat
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RSA, one of the public key cryptographies, is the most widely used for a wide variety of information systems. Especially, a compact, high-performance RSA LSI is highly desired for mobile applications, such as a smart card and a cellular phone. This paper describes a RSA cryptography co-processor LSI. It can process up to 2048-bit key data, which is required to guarantee the high security level of RSA. Although a large computational complexity is required to process 2048-bit RSA, our proposed N bit-wise modular multiplier based on Montgomery multiplication algorithm enables to reduce 25% circuit amount compared with the conventional one. A chip capable of operating at 60 MHz was fabricated using 0.18 mum TSMC CMOS technology. A total of 98.5 k gates (incl. SRAM and I/O modules) have been integrated into a 2.2 times 2.2 mm chip. Evaluation result with IC test system shows that power dissipation is 61.5 mW when 2048-bit RSA processing is operated at 40 MHz. This RSA LSI will make a significant contribution to the development of compact, high-performance secure information systems

Published in:

2006 International Symposium on VLSI Design, Automation and Test

Date of Conference:

26-28 April 2006