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Power-Gating Schemes for Ultra-Thin SOI (UTSOI) Circuits in Hybrid SOI-Epitaxial CMOS Structures

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4 Author(s)
Shih-Hsien Lo ; IBM T. J. Watson Res. Center, Yorktown Heights, NY ; Das, K.K. ; Ching-Te Chuang ; Sleight, J.W.

Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving active-mode performance, and reducing virtual supply bounce and standby leakage power is demonstrated

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006