Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Power-Gating Schemes for Ultra-Thin SOI (UTSOI) Circuits in Hybrid SOI-Epitaxial CMOS Structures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
Shih-Hsien Lo ; IBM T. J. Watson Res. Center, Yorktown Heights, NY ; Das, K.K. ; Ching-Te Chuang ; Sleight, J.W.

Several novel schemes of implementing MTCMOS circuits in hybrid UTSOI-epitaxial CMOS structures are proposed and analyzed through comprehensive circuit simulations. The schemes offer intrinsic high circuit density and facilitate header/footer body biasing techniques for performance enhancement and leakage reduction. The effectiveness in improving active-mode performance, and reducing virtual supply bounce and standby leakage power is demonstrated

Published in:

VLSI Design, Automation and Test, 2006 International Symposium on

Date of Conference:

26-28 April 2006