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Design of CMOS Ternary Latches

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3 Author(s)
Xiaoqiang Shou ; Linear Technol. Corp, North Chelmsford, MA ; Kalantari, N. ; Green, M.M.

This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-mum CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:53 ,  Issue: 12 )