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A Design Technique for Energy Reduction in NORA CMOS Logic

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4 Author(s)
Limniotis, K. ; Dept. of Informatics & Telecommun., Nat. & Kapodistrian Univ. of Athens ; Tsiatouhas, Y. ; Haniotakis, T. ; Arapoyanni, A.

In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-mum CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:53 ,  Issue: 12 )

Date of Publication:

Dec. 2006

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