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Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

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8 Author(s)
Zhuoyuan Li ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing ; Xianlong Hong ; Qiang Zhou ; Yici Cai
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Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:53 ,  Issue: 12 )

Date of Publication:

Dec. 2006

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