By Topic

Design of a Redundant Paralleled Voltage Regulator Module System with Improved Efficiency and Dynamic Response

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Santanu K. Mishra ; International Rectifier, Rhode Island IC Design Center, 200 Circuit Drive, North Kingstown, RI 02852. Phone: 401-667-0238, Fax: 401-667-0240, Email: smishra1@irf.com ; Steve Zhou ; Wenkang Huang ; George Schuellein

This paper discusses the design of true redundant, N+l parallel voltage regulator module (VRM) system with low droop resistance. Average current mode control and limited gain for voltage compensation is used to achieve droop current sharing between parallel modules without single point failure. Small signal model of the current sharing scheme is derived and experimentally validated. A novel local sense feedback is used to improve the dynamic performance of the parallel system. Experimental results from a prototype confirm the current sharing between two VRMs to be within 10 % and the dynamic response improvement by 33 % due to local sense feedback

Published in:

Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting  (Volume:5 )

Date of Conference:

8-12 Oct. 2006