Skip to Main Content
An all-digital symbol timing recovery technique that uses a 1-bit ADC, delay-XOR unit and a digital prefilter before the all-digital loop is analyzed. This approach provides a low-power, all-digital implementation in CMOS integrated circuit and exhibits very low jitter. The prefilter is arranged to eliminate frequency offsets on the input signal. The system is robust against fast and large Doppler shift and is therefore well suited for receivers in satellite applications. A symbol timing circuit based on this technique has been implemented for a wide range of bit rates (0.1-100 Kbps). It is synchronized within 3 or 4 bits in the presence of high carrier frequency offsets. A detailed performance study is carried out by both analytical simulation and hardware implementation to provide guidelines when the proposed scheme is applied to other transmission systems.
Communications, 2006. ICC '06. IEEE International Conference on (Volume:7 )
Date of Conference: June 2006