By Topic

Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

This paper presents a new memory-addressing scheme for the realization of power-efficient memory-based FFT processors. The scheme is based on the minimization of the coefficient access and reduction of switching activity by modifying the butterfly sequence. It also results in reducing hardware scale and shortening the critical path delay. Therefore, the power consumption in complex multiplier and memory is reduced

Published in:

Communications, 2006. APCC '06. Asia-Pacific Conference on

Date of Conference:

Aug. 2006