By Topic

Neural Network Approach for Multiple Fault Test of Digital Circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Pan Zhongliang ; Dept. of Electron., South China Normal Univ., Guangzhou ; Chen Ling ; Liu Shouqiang ; Zhang Guangzhao

A new approach for detecting multiple faults in digital circuits is presented in this paper, which uses neural network technique to generate the test vectors and to diagnose the multiple faults. First of all, the optimal neural network model corresponding to an arbitrary digital circuit is used. For a logic circuit with m inputs and n outputs, the optimal neural networks having m+n neurons can represent the logic function of the circuit. Secondly, the test vectors of multiple faults in the circuit are obtained by using evolutionary strategies to compute the minimum energy states of the optimal neural network. Thirdly, the multi-layer feed forward network and back propagation algorithm are used to diagnose the multiple faults in the circuit. The design of both network configurations and samples patterns are given in detail. Experimental results show that the approaches proposed in this paper are effective for detecting and diagnosing multiple faults in digital circuits

Published in:

Intelligent Systems Design and Applications, 2006. ISDA '06. Sixth International Conference on  (Volume:3 )

Date of Conference:

16-18 Oct. 2006