By Topic

CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Dai, S. ; Dept. Comput. Sci., California Univ., Irvine, CA ; Bozorgzadeh, E.

In this work, the goal is to develop a flexible CAD tool by which designers can explore integration of different types of embedded hard cores and interfaces in the FPGA architectures. Our tool takes a RTL design and defined embedded hard cores. The authors have modified VPR for place and route with embedded blocks. We have experimented different modules to be embedded as hard cores on a FPGA device. We also explore the FPGA routing architecture with embedded hard cores by applying uniform and non-uniform routing channels. In many cases, non-uniform channels produce more area-efficient architectures. Our results show that there is a need for a tool for better exploration of design space for FPGAs with embedded hard cores

Published in:

Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on

Date of Conference:

24-26 April 2006