By Topic

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Lucas, J.M. ; Dept. of Electr. & Comput. Eng., Pittsburgh Univ., PA ; Hoare, R. ; Kourtev, I.S. ; Jones, A.K.

This paper describes LURU, a methodology for FPGA combinational technology mapping through the parallel search capability of content-addressable memory (CAM). An overview was shown. First, a circuit is partitioned into a set of subcircuits. Topologies of these subcircuits are described using textual string representations. A precomputed set of strings for the circuit topologies that can be contained in a LUT of K or fewer inputs can be matched against the circuit representation in parallel using the CAM . By using CAM, the search space is increased over traditional technology mapping algorithms. A final mapping is produced for an FPGA device consisting of a heterogeneous network of LUT's of K or fewer inputs

Published in:

Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on

Date of Conference:

24-26 April 2006