By Topic

A 60-GHz-Band \times 12-Multiplier MMIC With Reduced Power Consumption

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ito, M. ; Syst. Devices Res. Labs., NEC Corp., Shiga ; Kishimoto, S. ; Hamada, Y. ; Maruhashi, K.

This paper presents a 60-GHz-band times12 multiplier and its application to a transceiver module. The multiplier consists of a quadrupler and a following tripler. For low dc power consumption, gatewidths of field-effect transistors are optimized. A cascode amplifier is adopted to obtain required output power levels. The fabricated multiplier exhibits output power higher than 0 dBm from 57 to 62 GHz with input power higher than -10 dBm. Spurious harmonic suppressions up to the 20th order are larger than 20 dBc with a desired 12th signal at a frequency of 60 GHz. DC power consumption is 185 mW. A transmitter module with the multiplier is assembled using a flip-chip bonding technique. Bit error rate is measured using amplitude shift-keying modulation with a data rate over 1 Gb/s

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:54 ,  Issue: 12 )