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A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

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5 Author(s)
Dutta, H. ; University of Erlangen-Nuremberg, Germany ; Hannig, F. ; Teich, J. ; Heigl, B.
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Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design.

Published in:

Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on

Date of Conference:

Sept. 2006