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Architecture design of an H.264/AVC decoder for real-time FPGA implementation

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2 Author(s)
Warsaw, T. ; Harris Corp., Rochester, NY ; Lukowiak, M.

This paper discusses hardware development of a real-lime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse transform, and deblocking filter stages. A hardware architecture is also proposed for FPGA implementations of a complete video decoder

Published in:

Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on

Date of Conference:

Sept. 2006