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A programmable high performance processor using the residue number system and CMOS VLSI technology

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2 Author(s)
Hohne, R.A. ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA ; Siferd, R.

The authors describe the general architecture of RNS (residue number system) processors, the VLSI implementation of the associated hardware, and finally, an RNS processor designed by the authors. The 2-μm CMOS implementation of the processor performs a 16×16 b (signed or unsigned) multiply-accumulate with 32-b accuracy at clock speeds greater than 20-MHz. It is noted that the advantages of the RNS over traditional binary computers is mainly speed. This advantage comes at a cost of larger hardware size, with a reduction in design complexity and design time due to the use of programmable logic arrays in a VLSI environment. Signed or unsigned operations take the same amount of time, use the same basic hardware, and have roughly equal delays for addition, subtraction, and multiplication. The disadvantage of this approach is that it is difficult or impossible to perform magnitude comparisons, bitwise operations, or division while the number is in RNS format

Published in:

Aerospace and Electronics Conference, 1989. NAECON 1989., Proceedings of the IEEE 1989 National

Date of Conference:

22-26 May 1989