A Novel Methodology To Reduce Leakage Power In Differential Cascode Voltage Switch Logic Circuits

Subthreshold leakage current increases exponentially in deep-submicron processes and hence is a crucial factor in scaling down designs. Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, a novel technique that achieves cancellation of leakage effects in both the pull-up transistor (PUT) as well as the pull-down network (PDN) paths of DCVSL circuits is presented. It involves voltage balancing in these paths using sleep transistors. Experimental results show significant leakage power savings (average of 61X at a temperature of 27deg C) in DCVSL circuits employing this sleep circuitry when compared to standard DCVSL circuits. At any given temperature, using our methodology the leakage power loss for DCVSL circuits is constant. A 4.31X improvement (on an average) in leakage savings using our methodology was observed when compared with the traditional power-gating technique