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A System-level Network-on-Chip Simulation Framework with Analytical Interconnecting Wire Models

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2 Author(s)
Jinwen Xi ; Dept. of ECE, Michigan State Univ., East Lansing, MI ; Peixin Zhong

This paper presents a system-level network-on-chip simulation framework employing transaction-level communication fabric models, such as routers and links, to achieve high simulation speed and provide NoC's latency and throughput information. This framework integrates an analytical interconnecting wire model to estimate the wire delay and its overall influence to the system performance and power properties in early design stages. SystemC provides the infrastructure to integrate transaction-level NoC model and analytical wire model seamlessly, making it easy to refine. 6 deep-submicron CMOS processes from 180nm to 45nm are used to evaluate the performance/power of NoC considering the interconnecting wire models, and wire's latency is estimated to be ~5X more than the router's in sub-100nm processes, and it brings 33.1% in average bandwidth degradation. Temporal and spatial NoC power analysis with wire models under different traffics provides more power implications for designers in early design stages

Published in:

Electro/information Technology, 2006 IEEE International Conference on

Date of Conference:

7-10 May 2006

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