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A New Technique to Exploit Instruction-Level Parallelism for Reducing Microprocessor Power Consumption

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2 Author(s)
Youssfi, Z. ; Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI ; Shanblatt, M.

A large portion of the power consumed by a high-performance out-of order microprocessor is attributed to units within the instruction window pipeline stages, from dispatch to commit. Power consumed within the window, and by the overall processor, is reduced by dynamic size adjustment of those units based on program needs. In this article, we introduce a new metric for estimating the instruction level parallelism (ILP) for a group of instructions using a simple ratio of the longest data dependence path's length to the total number of instructions in the group, hence referred to as the longest dependence path ratio (LDPR). We couple this concept with a design where units in the instruction window are divided into segments that are dynamically disabled for power savings when they are unused. The maximum number of enabled segments that a program can utilize is limited based on the amount of ILP estimated using the LDPR. We also show how measuring the LDPR is implemented by a simple extension to the dependence-check-logic at dispatch stage. Results using the LDPR show that power is saved with a minimal impact on performance, by reducing the number of available segments, not only in low ILP periods, but also over those having very high ILP. Using the Wattch power models and the MinneSPEC benchmarks, the LDPR implementation achieves an average of 36.5% of window power savings and 11% overall processor power savings, and with an average performance loss of a very modest 1.9%

Published in:

Electro/information Technology, 2006 IEEE International Conference on

Date of Conference:

7-10 May 2006