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Scalable Security Processor Design and Its Implementation

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4 Author(s)
Chen-Hsing Wang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu ; Jen-Chieh Yeh ; Chih-Tsun Huang ; Cheng-Wen Wu

This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT (design for test) platform is also implemented for the design-test integration. The security processor has been fabricated (using UMC 0.18mum CMOS technology) and measured. The core area is 3.899mm times 2.296mm (525K gates approximately) and the operating clock rate is 66MHz

Published in:

Asian Solid-State Circuits Conference, 2005

Date of Conference:

Nov. 2005

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