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Design of a High-Performance Switch for Circuit-Switched On-Chip Networks

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2 Author(s)
Chia-Ming Wu ; Dept. of Comput. Sci. & Inf. Eng., Nat. Dong Hwa Univ., Hualien ; Hsin-Chou Chi

System-on-a-chip (SoC) designs provide designers to integrate dozens of heterogeneous IP blocks together by a dedicated interconnect network. The major problems in the ultra deep sub-micron technology SoC design arise from the interconnection networks, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems might be mitigated by the network-on-chip (NoC) approach based on regular on-chip communication networks. In this paper, the authors propose the pre-scheduled circuit-switched network for NoC architectures. The authors have designed the switch supporting the network. Such architectures based on circuit switching with efficient buffer management can achieve guaranteed transmission latencies

Published in:

Asian Solid-State Circuits Conference, 2005

Date of Conference:

Nov. 2005