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A 231MHz, 2.18mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System

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4 Author(s)
Hyejung Kim ; Semiconductor System Laboratory, Department of Electrical Engineering and Computer Science, KAIST, Daejeon, Korea. ; Byeong-gyu Nam ; Ju-ho Sohn ; Hoi-jun Yoo

A 32-bit fixed-point logarithmic arithmetic unit is designed for mobile 3D graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in 2-cycle, and powering operation in 5-cycle. It uses programmable precision for accurate 3D pipeline computation and 8-region piecewise linear approximation model for logarithmic and exponential conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18mum CMOS technology with 9k gates. It operates at the maximum frequency of 231MHz and consumes 2.18mW

Published in:

2005 IEEE Asian Solid-State Circuits Conference

Date of Conference:

Nov. 2005