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Initial-On ESD Protection Design with PMOS-Triggered SCR Device

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2 Author(s)
Ming-dou Ker ; Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan. E-mail: mdker@ieee.org ; Shih-hung Chen

A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-mum CMOS process

Published in:

2005 IEEE Asian Solid-State Circuits Conference

Date of Conference:

Nov. 2005