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A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

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4 Author(s)
Mutsuo Daito ; Devices Technology Research Laboratories, SHARP Corporation, Tenri, Nara, Japan ; Hirofumi Matsui ; Masaya Ueda ; Kunihiko Iizuka

We present a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC) using a new digital distortion calibration technique. The calibration parameters are obtained using the same system as the conventional digital gain calibration. The ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. With the calibration it achieves 15-dB improvement of the third-order nonlinearity. The measured SNDR and SFDR are 71.6 dB and 82.3 dB respectively

Published in:

2005 IEEE Asian Solid-State Circuits Conference

Date of Conference:

Nov. 2005