By Topic

The Influence of a Novel Contacted Polysilicon-Filled Deep Trench (DT) Biased Structure and Its Voltage Bias State on CMOS Latchup

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Voldman, S.H. ; IBM Microelectron.

The discrepancy between polysilicon-filled deep trench (DT) isolation and trench isolation (TI) CMOS latchup immunity is addressed; this paradox is analyzed using by electrically connecting the poly-silicon region of the deep trench (DT) structure. With the ability to electrically bias the poly-silicon region within the deep trench structure, CMOS latchup is analyzed for the state of high bias, floating and grounding of the trench isolation structure. The novel structure was implemented into a 0.13-mum BiCMOS technology with a 200 GHz fT BiCMOS SiGeC HBT device. Experimental results show that CMOS latchup is modulated by the trench voltage bias state. Key latchup metrics, such as turn-on, trigger, and holding voltage will be shown. With trench voltage bias, CMOS latchup turn-on voltage remains unchanged, but the latchup trigger state varies from 40 V to 80 V. This has significant ramifications to CMOS latchup in BiCMOS Silicon Germanium technology, automotive applications, power electronics, as well as space applications

Published in:

Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International

Date of Conference:

26-30 March 2006