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On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships

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2 Author(s)
Harmanani, H.M. ; Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos ; Salamy, H.A.

This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method handles SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. The authors present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time

Published in:

Circuits and Systems, 2006 IEEE North-East Workshop on

Date of Conference:

18-21 June 2006