A Low-Power Pipelined CAM for High-Performance IP Routing

Packet switched networks such as the Internet require efficient IP routing in order to manage the traffic flows. In these environments CAM memories play a key role because they provide the address resolution time. This paper presents a practical implementation of a low-power CAM oriented to high-performance IP routing. The architecture devised shows optimal results in terms of area, speed and power consumption for these search-based applications by proposing a pipelined implementation split into banks with a reduction of the parameter word. Experimental results show how the proposed architecture provides significant improvements in terms of power and speed