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As silicon manufacturing processes scale to and beyond the 65-nm node, process variations are consuming an increasingly larger portion of design and test budgets. Such variations play a significant part in subthreshold leakage and other important device performance metrics. The rise in inherent systematic and random nonuniformity as we scale our silicon devices to the level of atomic scaling will have far-reaching effects on every aspect of design, manufacturing, test, and overall reliability. This special issue explores this subject from different perspectives: process monitoring, testing, adaptive circuits, and architecture changes.